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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\git\TangMega-138KPro-example\ddr_test\Hynix_400MHz\src\sdio_fifo_send\temp\FIFO\fifo_define.v<br>
D:\git\TangMega-138KPro-example\ddr_test\Hynix_400MHz\src\sdio_fifo_send\temp\FIFO\fifo_parameter.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\FIFO\data\edc.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\FIFO\data\fifo.v<br>
K:\downloads\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64_win\Gowin_V1.9.11_x64\IDE\ipcore\FIFO\data\fifo_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.11 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5AST-LV138FPG676AES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5AST-138</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Apr 25 13:52:31 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>sdio_fifo_send</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.67s, Elapsed time = 0h 0m 0.679s, Peak memory usage = 87.531MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 87.531MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 87.531MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 87.531MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 87.531MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.608s, Elapsed time = 0h 0m 0.659s, Peak memory usage = 108.141MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.141s, Peak memory usage = 108.211MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 108.211MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 108.211MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>90</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>90</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>46</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>44</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>82</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>80</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>100</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>41</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>28</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>128(100 LUT, 28 ALU) / 138240</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>82 / 139140</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 139140</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>82 / 139140</td>
<td><1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>2 / 340</td>
<td><1%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>1</td>
<td>RdClk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>RdClk_ibuf/I </td>
</tr>
<tr>
<td>2</td>
<td>WrClk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>WrClk_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>RdClk</td>
<td>100.000(MHz)</td>
<td>145.375(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>WrClk</td>
<td>100.000(MHz)</td>
<td>134.116(MHz)</td>
<td>10</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.544</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.805</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Equal.wq2_rptr_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Almost_Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>WrClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>WrClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wq2_rptr_6_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/Equal.wq2_rptr_6_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_6_s1/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>fifo_inst/Equal.rcount_w_6_s1/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_3_s0/I3</td>
</tr>
<tr>
<td>2.487</td>
<td>0.289</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>fifo_inst/Equal.rcount_w_3_s0/F</td>
</tr>
<tr>
<td>2.900</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_2_s0/I1</td>
</tr>
<tr>
<td>3.468</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rcount_w_2_s0/F</td>
</tr>
<tr>
<td>3.880</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_2_s/I1</td>
</tr>
<tr>
<td>4.480</td>
<td>0.600</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>4.480</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>4.530</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>4.530</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>4.580</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>4.580</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>4.630</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>4.630</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>4.680</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_6_s/COUT</td>
</tr>
<tr>
<td>4.680</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_7_s/CIN</td>
</tr>
<tr>
<td>4.730</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_7_s/COUT</td>
</tr>
<tr>
<td>4.730</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/wcnt_sub_8_s/CIN</td>
</tr>
<tr>
<td>4.780</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wcnt_sub_8_s/COUT</td>
</tr>
<tr>
<td>5.193</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s6/I3</td>
</tr>
<tr>
<td>5.481</td>
<td>0.289</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s6/F</td>
</tr>
<tr>
<td>5.894</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s4/I0</td>
</tr>
<tr>
<td>6.473</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s4/F</td>
</tr>
<tr>
<td>6.885</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s0/I2</td>
</tr>
<tr>
<td>7.393</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/awfull_val_s0/F</td>
</tr>
<tr>
<td>7.805</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Almost_Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.710, 50.186%; route: 3.300, 44.640%; tC2Q: 0.382, 5.174%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.121</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.228</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>RdClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>RdClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>fifo_inst/Empty_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_2_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>fifo_inst/rbin_num_next_2_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_5_s5/I1</td>
</tr>
<tr>
<td>2.766</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>fifo_inst/rbin_num_next_5_s5/F</td>
</tr>
<tr>
<td>3.179</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_6_s3/I1</td>
</tr>
<tr>
<td>3.746</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rbin_num_next_6_s3/F</td>
</tr>
<tr>
<td>4.159</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rgraynext_5_s1/I2</td>
</tr>
<tr>
<td>4.666</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/Equal.rgraynext_5_s1/F</td>
</tr>
<tr>
<td>5.079</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/n222_s0/I0</td>
</tr>
<tr>
<td>5.674</td>
<td>0.595</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/n222_s0/COUT</td>
</tr>
<tr>
<td>5.674</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/n223_s0/CIN</td>
</tr>
<tr>
<td>5.724</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/n223_s0/COUT</td>
</tr>
<tr>
<td>5.724</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/n224_s0/CIN</td>
</tr>
<tr>
<td>5.774</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/n224_s0/COUT</td>
</tr>
<tr>
<td>5.774</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/n225_s0/CIN</td>
</tr>
<tr>
<td>5.824</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/n225_s0/COUT</td>
</tr>
<tr>
<td>6.236</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rempty_val_s1/I0</td>
</tr>
<tr>
<td>6.815</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rempty_val_s1/F</td>
</tr>
<tr>
<td>7.228</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.545, 52.017%; route: 2.887, 42.370%; tC2Q: 0.382, 5.613%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.167</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.181</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Equal.rq2_wptr_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Almost_Empty_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>RdClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>RdClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rq2_wptr_7_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>fifo_inst/Equal.rq2_wptr_7_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wcount_r_6_s1/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>fifo_inst/Equal.wcount_r_6_s1/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wcount_r_3_s0/I3</td>
</tr>
<tr>
<td>2.487</td>
<td>0.289</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>fifo_inst/Equal.wcount_r_3_s0/F</td>
</tr>
<tr>
<td>2.900</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wcount_r_2_s0/I1</td>
</tr>
<tr>
<td>3.468</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wcount_r_2_s0/F</td>
</tr>
<tr>
<td>3.880</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rcnt_sub_2_s/I0</td>
</tr>
<tr>
<td>4.475</td>
<td>0.595</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>fifo_inst/rcnt_sub_2_s/COUT</td>
</tr>
<tr>
<td>4.475</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>fifo_inst/rcnt_sub_3_s/CIN</td>
</tr>
<tr>
<td>4.525</td>
<td>0.050</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>fifo_inst/rcnt_sub_3_s/COUT</td>
</tr>
<tr>
<td>4.525</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rcnt_sub_4_s/CIN</td>
</tr>
<tr>
<td>4.575</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rcnt_sub_4_s/COUT</td>
</tr>
<tr>
<td>4.575</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rcnt_sub_5_s/CIN</td>
</tr>
<tr>
<td>4.625</td>
<td>0.050</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rcnt_sub_5_s/COUT</td>
</tr>
<tr>
<td>4.625</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/rcnt_sub_6_s/CIN</td>
</tr>
<tr>
<td>4.869</td>
<td>0.244</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rcnt_sub_6_s/SUM</td>
</tr>
<tr>
<td>5.281</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/arempty_val_s2/I2</td>
</tr>
<tr>
<td>5.789</td>
<td>0.507</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/arempty_val_s2/F</td>
</tr>
<tr>
<td>6.201</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/arempty_val_s0/I1</td>
</tr>
<tr>
<td>6.769</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/arempty_val_s0/F</td>
</tr>
<tr>
<td>7.181</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Almost_Empty_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Almost_Empty_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Almost_Empty_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 3.499, 51.690%; route: 2.887, 42.659%; tC2Q: 0.382, 5.651%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.188</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.161</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Equal.wbin_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Full_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>WrClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>WrClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wbin_2_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>fifo_inst/Equal.wbin_2_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_5_s2/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>fifo_inst/Equal.wgraynext_5_s2/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_5_s1/I0</td>
</tr>
<tr>
<td>2.778</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.wgraynext_5_s1/F</td>
</tr>
<tr>
<td>3.190</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wfull_val_s2/I0</td>
</tr>
<tr>
<td>3.769</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wfull_val_s2/F</td>
</tr>
<tr>
<td>4.181</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wfull_val_s0/I1</td>
</tr>
<tr>
<td>4.749</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/wfull_val_s0/F</td>
</tr>
<tr>
<td>5.161</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Full_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>WrClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>WrClk_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>WrClk_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Full_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Full_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.199</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.150</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.349</td>
</tr>
<tr>
<td class="label">From</td>
<td>fifo_inst/Empty_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>fifo_inst/Equal.rptr_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>RdClk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>RdClk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>0.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Empty_s0/CLK</td>
</tr>
<tr>
<td>0.795</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>fifo_inst/Empty_s0/Q</td>
</tr>
<tr>
<td>1.207</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_2_s4/I0</td>
</tr>
<tr>
<td>1.786</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>fifo_inst/rbin_num_next_2_s4/F</td>
</tr>
<tr>
<td>2.199</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_5_s5/I1</td>
</tr>
<tr>
<td>2.766</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>fifo_inst/rbin_num_next_5_s5/F</td>
</tr>
<tr>
<td>3.179</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/rbin_num_next_7_s5/I0</td>
</tr>
<tr>
<td>3.758</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>fifo_inst/rbin_num_next_7_s5/F</td>
</tr>
<tr>
<td>4.170</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rgraynext_7_s0/I1</td>
</tr>
<tr>
<td>4.738</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>fifo_inst/Equal.rgraynext_7_s0/F</td>
</tr>
<tr>
<td>5.150</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rptr_7_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>RdClk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>RdClk_ibuf/I</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tINS</td>
<td>RR</td>
<td>43</td>
<td>RdClk_ibuf/O</td>
</tr>
<tr>
<td>10.413</td>
<td>0.413</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>fifo_inst/Equal.rptr_7_s0/CLK</td>
</tr>
<tr>
<td>10.349</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>fifo_inst/Equal.rptr_7_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.293, 48.390%; route: 2.063, 43.536%; tC2Q: 0.382, 8.074%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.413, 100.000%</td></tr>
</table>
<br/>
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